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PDH for Telecommunication Network-电信网络中的PDH技术-(英文)

PDH for Telecommunication Network-电信网络中的PDH技术-(英文)

作者:孙玉
出版社:人民邮电出版社出版时间:2017-09-01
开本: 32开 页数: 386
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PDH for Telecommunication Network-电信网络中的PDH技术-(英文) 版权信息

PDH for Telecommunication Network-电信网络中的PDH技术-(英文) 本书特色

This book is a basic work specialized on modern digital communication, which consists of plesiochronous digital hierarchy, digital multiplexing principle, essential realization technology, relevant recommendations of ITU, CCITT/TSS and the application design of typical engineering project. It is intended for communication engineers and technicians as well as teachers and students of the universities and colleges.

PDH for Telecommunication Network-电信网络中的PDH技术-(英文) 内容简介

作者为知名资 深院士,本英文版的主要内容基于作者中文著作《数字复接技术》,是作者在通信研究所数字网专业多年工作成果及相关专题讲座内容的集结。

PDH for Telecommunication Network-电信网络中的PDH技术-(英文) 目录

Chapter 1 Introduction 1

1.1 DIGITAL MULTIPLEX CONCEPT 1

1.2 DIGITAL MULTIPLEX HIERARCHY 3

1.3 CCITT RECOMMENDATIONS 5

1.4 CONTENT OF THE BOOK 6

Chapter 2 Synchronous Multiplexing 7

2.1 SYNCHRONOUS MULTIPLEXING EQUIPMENT COMPOSITION 7

2.2 FRAME STRUCTURE 9

2.3 FRAME ALIGNMENT 11

2.4 SYNCHRONIZATION ACQUISITION METHOD 13

2.5 THE CODE TYPE OF FRAME ALIGNMENT SIGNALS 15

2.6 AVERAGE ACQUISITION TIME 16

2.7 OPTIMUM LENGTH OF FRAME ALIGNMENT SIGNAL 20

2.8 SYNCHROMIZATION STATUS PROTECTION 24

2.9 ACQUISITION PROCEDURE CHECKING 27

2.10 FRAME ALIGNMENT PROTECTION PARAMETERS 31

2.11 AVERAGE OUT-OF-FRAME TIME AND AVERAGE SYNCHRONIZATION TIME 34

2.12 THE BIT ERRORS OF SYNCHRONIZATION OUT-OF-FRAME 35

2.13 FRAME ALIGNMENT ACQUISITION/ MAINTENANCE LOGIC 37

2.14 GUARANTEEING THE SYNCHRONIZATION CIRCUMSTANCE 41

2.15 CCITT RECOMMENDATIONS 44

Chapter 3 Positive Justification 49

3.1 PLESIOCHRONOUS MULTIPLEX 49

3.2 PRINCIPLE OF POSITIVE JUSTIFICATION 50

3.3 BASIC FORMULA OF POSITIVE JUSTIFICATION 52

3.4 JUSTIFICATION DESIGN 54

3.5 JUSTIFICATION TRANSITION PROCESS 57

3.6 THE CHANGE RANGE OF THE READ/WRITE TIME DIFFERENCE IN A

STABLE JUSTIFICATION PROCESS 61

3.7 CLASSIFICATION OF JUSTIFICATION TRANSITION PROCESS 64

3.8 BIT RATE RECOVERY DESIGN 66

3.9 PHASE-LOCK PARAMETERS DESIGN 69

3.10 VOLTAGE CONTROLLED OSCILLATOR DESIGN 73

3.11 BUFFER SIZE 76

3.12 CCITT Recommendations 78

Chapter 4 Impairment of Positive Justification 82

4.1 STUFFING JITTER 82

4.1.1 Physical Concept of Stuffing Jitter 82

4.1.2 Signal justification process justifying only q times in p frames 84

4.1.3 Justifying q times in p frames with a residue 88

4.1.4 The relationship between the number of code justification detectors and

stuffing jitter 95

4.1.5 Distribution of stuffing jitter 99

4.2 STUFFING ERROR 104

4.2.1 Physical Concept of Stuffing Error 104

4.2.2 Calculation of stuffing error 104

4.2.3 Suppression of stuffing errors 109

Chapter 5 Positive/Negative Justification 111

5.1 THE PRINCIPLE OF POSITIVE/NEGATIVE JUSTIFICATION 111

5.2 JUSTIFICATION BY FIX ED DECISION CONTROL 113

5.3 ADAPTIVE JUSTIFICATION CONTROL 116

5.4 POSITIVE/NEGATIVE JUSTIFICATION CONTROL CIRCUIT 124

5.5 TRANSITION PROCESS OF JUSTIFICATION 126

5.6 PARAMETER DESIGN OF JUSTIFICATION 128

5.7 ENVIRONMENT DESIGN OF JUSTIFICATION 131

5.8 THE TECHNICAL APPLICATION OF THE POSITIVE/NEGATIVE

JUSTIFICATION 135

5.9 EXAMPLE OF POSITIVE/NEGATIVE JUSTIFICATION DESIGN 136

5.10 CHARACTERISTIC COMPAISON OF JUSTIFICATIONS 142

5.11 RECOMMENDATION OF CCITT 143

Chapter 6 Positive/0/Negative Justification 145

6.1 CONCEPT OF POSITIVE/0/NEGATIVE JUSTIFICATION 145

6.2 THE PRINCIPLES OF DELTA CONTROLLED POSITIVE/0/NEGATIVE

JUSTIFICATION 146

6.3 DIGITAL SMOOTH POSITIVE/0/NEGATIVE JUSTIFICATION

PRINCIPLES 147

6.4 FRAME STRUCTURE 149

6.5 JUSTIFICATION AND RECOVERY CONTROL 153

6.6 JUSTIFICATION TRANSITION PROCESS 156

6.7 DIGITAL SMOOTH 162

6.8 PULSE SMOOTHLY PRINCIPLE OF WEST GERMAN PCM30D 163

6.9 AUSTRALlA 2/8Mbit/s MULTIPLEXER PULSE SMOOTH

PRINCIPLE 166

6.10 ENGINEERING APPLICATIONS OF POSITIVE/0/NEGATIVE

JUSTIFICATION 169

Chapter 7 Measurement Techniques of Justification 170

7.1 MEASUREMENT OF STUFFING JITTER 170

7.1.1 Characteristics of stuffing jitter 170

7.1.2 Measurement range and precision requirement 172

7.1.3 Measurement equipment 173

7.1.4 Measurement method 176

7.1.5 Example of measurement 181

7.2 MEASUREMENT OF MULTIPLEX CODE ERROR 183

7.2.1 Characteristics of multiplex code error 183

7.2.2 Requirements of code error meter 184

7.2.3 Design of Special code error meter 186

7.2.4 Design of analog channel 189

7.2.5 Example of measurement 190

7.3 MEASUREMENT CHARACTERISTICS OF THE PHASE-LOCKED LOOP OF

THE CODE RECOVERY 192

7.3.1 Tracing error measurement 192

7.3.2 Measurement of jitter suppression characteristics 194

Chapter 8 Frame Adjustment Principle 195

8.1 GENERAL 195

8.2 FRAME REGULATION CATEGORIES 198

8.3 THE WORKING PRINCIPLE OF PRE-BUFFER FRAME REGUL

ATOR 199

8.4 2048kbit/s FRAME REGULATOR DESIGN 203

8.5 THE ADDITIONAL FUNCTION OF FRAME REGULATOR 210

Chapter 9 PDH/SDH Interface 211

9.1 GENERAL 211

9.2 HIGHER ORDER GROUP SDH 211

9.3 THE GENERAL ARRANGEMENT OF PDH/SDH INTERFACE 214

9.4 THE ARRANGEMENT DESIGN FOR C-4 TO ENTER STM-1 217

9.5 THE ARRANGEMENT DESIGN FOR C-3 ENTERING STM-1 221

9.6 THE ARRANGEMENT DESIGN FOR TUG ENTERING HIGH

ORDER VC 224

9.7 BASIC CONTAINER ENTERING TUG 227

9.8 STM-N MULTIPLEXING 231

9.9 PAYLOAD CONTAINER INTERFACE IN CCITT REC 234

9.10 THE IMPROVED DESIGN OF PAYLOAD CONTAINER

INTERFACE 240

Chapter 10 Anti Fading Frame Synchronization 248

10.1 THE PRINCIPLES OF ANTI FADING FRAME SYNCHRONIZATION 248

10.2 FRAME SYNCHRONIZATION AVERAGE KEEPING TIME 253

10.2.1 Scheme (1) 253

10.2.2 Scheme (2) 255

10.2.3 Scheme (3) 257

10.2.4 Scheme (4) 261

10.2.5 Scheme (5) 265

10.2.6 Scheme (6) 269

10.3 FRAME LOSS AVERAGE KEEPING TIME 273

10.3.1 Frame Loss deciding Time 273

10.3.2 Frame Synchronization Search Time 275

10.3.3 Frame Synchronization Deciding Time 278

10.3.4 Frame Synchronization Reset Delay 285

10.3.5 Frame Loss Keeping Time 286

10.4 COMPARISON OF FRAME SYNCHRONIZATION SCHEMES 286

10.4.1 Frame Synchronization Average Keeping Time 286

10.4.2 Frame Loss Average Keeping Time 289

10.4.3 The Synthetical Criterion of the Frame Synchronization System 293

Chapter 11 Engineering Application Design 296

11.1 GENERAL PLESIOCHRONOUS GROUP MULTIPLEX DESIGN 296

11.1.1 Elementary Parameters Design 296

11.1.2 Transition Process Design 300

11.1.3 Frame Loss Probability and Search Characteristics Design 300

11.1.4 Partition of the Basic Units 301

11.1.5 Design Examples 302

11.2 STANDARD/NON-STANDARD RATES TOLERANCE DESIGN 307

11.2.1 Introduction 307

11.2.2 Transmission of Non-Standard Binary Digits through Standard Channels 308

11.2.3 Design Examples 309

11.2.4 Compatible Multiplex of Different Tributary Rates 310

11.3 PLESIOCHRONOUS/SYNCHRONOUS COMPATIBLE DESIGN 313

11.3.1 Introduction 313

11.3.2 Instruction Justification Compatible method 313

11.3.3 Multiframe Fixed Control Compatible Method 316

11.4 2/34Mbit/s MULTIPLEX DESIGN 320

11.4.1 2/34Mbit/s Multiplex Scheme Comparison 320

11.4.2 Model B 2/34Mbit/s Multiplexer Design 323

11.4.3 CCITT Recommendations 329

11.5 DESIGN OF BRANCH IN GROUP TRUNK TRANSMISSION 329

11.5.1 Introduction 329

11.5.2 Trunk Branch Simplified Scheme One 331

11.5.3 Trunk Branch Simplified Scheme Two 331

11.5.4 Trunk Branch Simplified Scheme Three 332

11.5.5 Design of Branch Control Signals 335

11.5.6 Function Supplement 337

11.5.7 CCITT Recommendations 339

11.6 INTERNETWORK MULTIPLEX DESIGN 341

11.6.1 2048-6312kbit/s Interconnection Multiplex Design 341

11.6.2 44 736-139 264kbit/s Interconnection Multiplex Design 343

11.7 SUBGROUP MULTIPLEX DESIGN 346

11.7.1 Subgroup Rate Selection 346

11.7.2 Subframe Structure Arrangement 349

11.7.3 Examples of Subgroup Frame Structure Design 355

11.8 ISDN USERS/NETWORK INTERFACE MULTIPLEX DESIGN 360

11.8.1 2B D Interface Multiplex Design 360

11.8.2 2048kbit/s Primary Interface Multiplex Design 362

11.8.3 Multiplex Design of Entering 64kbit/s Channel 363

11.8.4 Multiplex Design of X1 Rate Entering 8/16kbit/s 363

11.8.5 Design of V Rate Multiplexed into Middle Rate 366

11.9 DESIGN OF MULTIPLEX SYSTEM MAINTENANCE 371

11.9.1 Introduction 371

11.9.2 Maintenance Principles 371

11.9.3 Multiplexer Maintenance Requirements 373

11.9.4 System Consideration of Maintenance Design 375

11.9.5 Examples of Maintenance Design 376

Bibliography 382

出集出版后记 386

展开全部

PDH for Telecommunication Network-电信网络中的PDH技术-(英文) 作者简介

1962年毕业于清华大学,后被分配到中国电子科技集团第54研究所工作至今。其间,从事军事通信设备研制和通信系统总体工程设计;领导创建了电信网络专业和数字家庭专业;出版电信科技著作13部。1995年当选中国工程院院士。现任,国防电信网络重点实验室科技委主任;兼任,中央军委科技委顾问。

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